The present invention relates generally to semiconductor inspection and defect analysis techniques, and more specifically to techniques for reviewing (or analyzing) defects on the defect analysis apparatus.
Generally, the industry of semiconductor manufacturing involves highly complex techniques for fabricating integrating circuits using semiconductor materials. Due to the large scale of circuit integration and the decreasing size of semiconductor devices, the semiconductor manufacturing process is prone to processing defects. Testing procedures are therefore critical to maintain quality control. Since the testing procedures are an integral and significant part of the manufacturing process, the semiconductor industry is constantly seeking more accurate and efficient testing procedures.
An optical inspection tool is commonly used to detect defects. Typical inspection processes detect defects by comparing similar semiconductor device areas on a wafer (e.g., die-to-die or cell-to-cell). The differences detected between the two device areas can either be a defect, which can cause a device to function improperly, or a nuisance, which will not affect system operations. An integral phase of semiconductor wafer inspection involves optimizing the settings, commonly referred to as the “recipe,” of an inspection device so that it can accurately distinguish defects from nuisances.
After potential defects are found by an inspection system, the wafer is typically transferred to a review tool or a metrology tool. In general, the review tool and metrology tool have a significantly higher resolution than the inspection tool. This higher resolution is needed to analyze or measure rather small defects. A scanning electron microscopy (SEM) system is typically used as a review tool to provide high resolution images of defects for examination.
When the wafer is transferred to a review tool (or metrology tool), a defect file is also usually sent to the review tool. The inspection defect file typically includes the coordinates of each defect so that the review tool can automatically move to each of the locations on the wafer and image each defect (or nuisance) found at each location. An operator then reviews a sampling of the defects and classifies such defects. The operator then uses the classification information to determine whether the inspection tool is set up correctly or can be improved, e.g., so that important defects are substantially captured while a minimum number of nuisance errors are captured. If it is determined that the inspection tool is not set up correctly or can be improved, then an operator manually walks from the review station to the inspection station to then adjust the recipe of the inspection tool. The wafer is also transferred back to the inspection tool and defect data is once again collected under the new recipe settings. This procedure may be repeated any number of times until the operator at the review station determines that the inspection tool is set up correctly. Thus, setting up the inspection tool can be a rather tedious and time consuming procedure, which requires an operator to walk back and forth between the inspection station and the review station.
Additionally, the defect information from the inspection tool that is typically available at the review tool is very limited. It only provides the review tool with a mechanism for stepping to each defect location and little else. The defect information does not include any other contextual information, such as the inspection defect patches, which may aid defect analysis procedures at the review tool.
In view of the foregoing, it would be desirable to have a richer amount of defect information from the inspection tool available at the review tool so as to facilitate procedures implemented at the defect review tool. Additionally, improved apparatus and techniques for efficiently setting up the inspection tool are needed.